Nodes in a shared multiprocessor computing system generally cache data (from main memory) that may be accessed by other nodes in the system. When a node changes the data stored in such shared memory, however, all other nodes sharing (i.e., caching) such data should be notified of the change (e.g., via invalidation or updating processes) to ensure data coherency. If not notified of changes, the other nodes undesirably may use data that no longer is valid, thus corrupting system operation.
To mitigate this problem, “home nodes” in systems using directory based write invalidate protocols, for example, maintain a directory for tracking the global coherence state of cache lines that are mapped to its portion of the global memory. Such protocols, however, also permit other nodes (“producers”) to modify the data in these cache lines. In other words, a producer may modify data mapped to another node's portion of the global memory.
During use, some other node (a “consumer”) also may request access to data mapped to the home node's portion of the global memory space. Prior to the request, however, a producer node may have changed such data. In that case, to maintain coherency, the three nodes of interest (consumer, producer, and home nodes) all generate and transmit multiple messages throughout the system. Details of this process are described in the provisional United States patent application from which this application claims priority. Undesirably, these messages can unduly slow down system performance. Moreover, such prior art systems can cause remote read miss stalls. The effect of these messages is more pronounced in systems having many nodes (e.g., supercomputers having hundreds or thousands of nodes).